Evaluation of Resistance to TSWV and Agronomic Behaviour of Some TSWV-Resistant Tomato Genotypes in Southern Italy

A two-year research was carried out in Ofanto valley (Basilicata region, southern Italy) in 2006-2007, for evaluating agronomic behaviour of new processing tomato genotypes resistant to tomato spotted wilt virus (TSWV) and ascertaining their effective resistance to the virus. Five TSWV-resistant genotypes (cultivars and lines) were compared in each year the TSWV susceptible cultivar ‘Perfectpeel’ was used as a control. Two transplant dates were adopted in both years: 1) mean-early and 2) mean-late. A split-plot design with 3 reps was followed in the two years. Yield and fruit quality were considered as agronomic traits. About virological aspects, field observations and laboratory analysis (ELISA, IME) were carried out during crop cycles. Phytoplasma infection frequency was also assessed for the same plants. The control cultivar ‘Perfectpeel’ resulted highly productive in both years that were however characterized by low incidence of virus infections; beside, among new genotypes ‘Vespro’ and ‘Suerte’ gave a good yield, while ‘Candia’ and ‘Isi 23259’ exhibited high fruit quality. Virological studies showed that the new processing tomato genotypes were indeed TSWV-resistant. Finally, phytoplasma infections had a dissimilar incidence among plants of the tested genotypes

A Real-time Information System for Public Transport in Case of Delays and Service Disruptions

AbstractPromoting the use of public transportation and Intelligent Transport Systems, as well as improving transit accessibility for all citizens, may help in decreasing traffic congestion and air pollution in urban areas. In general, poor information to customers is one of the main issues in public transportation services, which is an important reason for allocating substantial efforts to implement a powerful and easy to use and access information tool. This paper focuses on the design and development of a real time mobility information system for the management of unexpected events, delays and service disruptions concerning public transportation in the city of Milan. Exploiting the information on the status of urban mobility and on the location of citizens, commuters and tourists, the system is able to reschedule in real time their movements. The service proposed stems from the state of the art in the field of travel planners for public transportation, available for Milan. Peculiarly, we built a representation of the city transit based on a time-expanded graph that considers the interconnections among all the stops of the rides offered during the day. The structure distinguishes the physical stations and the get on/get off stops of each ride, representing them with two different types of nodes. Such structure allows, with regard to the main focus of the project, to model a wide range of service disruptions, much more meaningful than those possible with approaches currently proposed by transit agencies. One of the most interesting point lies in the expressive capability in describing the different disruptions: with our model it is possible, for instance, to selectively inhibit getting on and/or off at a particular station, avoid specific rides, and model temporary deviations

Tunneling Trust Into the Blockchain: A Merkle Based Proof System for Structured Documents

The idea of Smart contracts foresees the possibility of automating contractual clauses using hardware and software tools and devices. One of the main perspectives of their implementation is the automation of interactions such as bets, collaterals, prediction markets, insurances. As blockchain platforms, such as Ethereum, offer very strong guarantees of untampered, deterministic execution, that can be exploited as smart contracts substrate, the problem of how to provide reliable information from the "outside world" into the contracts becomes central. In this article, we propose a system based on a Merkle tree representation of structured documents (such as all XML), with which it is possible to generate compact proofs on the content of web documents. The proofs can then be efficiently checked on-chain by a smart contract, to trigger contract action. We provide an end-to-end proof of concept, applying it to real use case scenarios, which allows us to give an estimate of the costs

preliminary studies on productivity of white pleurotus eryngii isolates in protected cultivation

Four isolates of Pleurotus eryngii species-complex, originating from different basidiomata growing in a mountainous area of the Basilicata region (southern Italy) and characterized by white pileus cuticle (Wh A, Wh B, Wh C, and Wh D) were compared, in artificial cultivation conditions, to other isolates of the same mushroom with beige (Be 3, Be 5) or brown cap (Br 1, Br 2) originating from the same area of the former or selected among the commercial ones (Com 142 and Com 164) in order to evaluate their productivity and morphological features. The experiments were carried out in a greenhouse belonging to the Faculty of Agriculture, University of Bari Aldo Moro, in autumn winter 2010-2011, using substrate bags well colonized by P. eryngii mycelium and kept at 4-6°C for 5 months. Wh A and Wh D and, less significantly, Wh C, Be 5 and Com 142, produced a fresh basidioma yield significantly higher than the five other tested isolates (Wh B, Be 3, Br 1, Br 2 and Com 164). Only Com 142 produced the basidiomata of medium and maximum size significantly heavier and with larger pileus diameter than other tested isolates. Com 142 also resulted significantly different, for the basidiomata number/substrate bag, from the white pileus cuticle isolates except for Wh B. All tested isolates concentrated almost all (90-95%) of the sporophore yield in the first basidioma flush. No significant differences were found among all tested P. eryngii isolates in terms of yield earliness

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication

Network-on-Chip (NoC) has emerged as a very promising paradigm for designing scalable communication architecture for Systems on Chips (SoCs). However, NoCs designed to fulfill the bandwidth requirements between the cores of an SoC for a certain set of running applications may be highly sub-optimal for another set of applications. In this context, methods that can lead to versatility enhancements of initial NoC designs to changing working conditions, imposed by variable sets of executed real-life applications at each moment in time, are very important for designing competitive NoCs in industrial SoCs. In this work, we present a run-time reconfigurable NoC framework based on the partial dynamic reconfiguration capabilities of Field- Programmable Gate Arrays (FPGAs). This new NoC framework can dynamically create/delete express lines between SoC components (implementing dynamically circuit-switching channels) and perform run-time NoC topology and routing-table reconfigurations to handle interconnection congestion, with a very limited performance overhead. Moreover, we show in our experimental results that the addition of these dynamic reconfiguration capabilities into basic NoCs using our framework only implies a very limited area overhead (around 10% on average) with respect to the initial NoC designs; thus, it can bring great benefits when compared to traditional non-reconfigurable NoC design approaches for worst-case bandwidth requirements in SoCs with many possible sets of running applications

Design Methods for Parallel Hardware Implementation of Multimedia Iterative Algorithms

Traditionally, parallel implementations of multimedia algorithms are carried out manually, since the automation of this task is very difficult due to the complex dependencies that generally exist between different elements of the data set. Moreover, there is a wide family of iterative multimedia algorithms that cannot be executed with satisfactory performance on Multi-Processor Systems-on-Chip or Graphics Processing Units. For this reason, new methods to design custom hardware circuits that exploit the intrinsic parallelism of multimedia algorithms are needed. As a consequence, in this paper, we propose a novel design method for the definition of hardware systems optimized for a particular class of multimedia iterative algorithms. We have successfully applied the proposed approach to several real-world case studies, such as iterative convolution filters and the Chambolle algorithm, and the proposed design method has been able to automatically implement, for each one of them, a parallel architecture able to meet real-time performance (up to 72 frames per second for the Chambolle algorithm), with on-chip memory requirements from 2 to 3 orders of magnitude smaller than the state-of-the art approaches

A High–Performance Parallel Implementation of the Chambolle Algorithm

The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has been faced using many different mathematical approaches. A large body of work has been recently published about variational methods, following the technique for total variation minimization proposed by Chambolle. Still, their hardware implementations do not offer good performances in terms of frames that can be processed per time unit, mainly because of the complex dependency scheme among the data. In this work, we propose a highly parallel and accelerated FPGA implementation of the Chambolle algorithm, which splits the original image into a set of overlapping sub-frames and efficiently exploits the reuse of intermediate results. We validate our hardware on large frames (up to 1024 × 768), and the proposed approach largely outperforms the state-of-the-art implementations, reaching up to 76× speedups as well as realtime frame rates even at high resolutions

Parallelizing the Chambolle Algorithm for Performance-Optimized Mapping on FPGA Devices

The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs), which are often employed to support the tasks of General Purpose Processors (GPP). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability of performing massive parallel computation. However, in order to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which is in general a very challenging task. This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based on GPUs, but barely improve the performance that can be obtained with a powerful GPP. In this paper, we propose a novel approach to extract the parallelism from computation-intensive multimedia algorithms, which includes an analysis of their dependency schema and an assessment of their data reuse. We then perform a thorough analysis of the Chambolle algorithm, providing a formal proof of its inner data dependencies and locality properties. Then, we exploit the considerations drawn from this analysis by proposing an architectural template that takes advantage of the fine-grained parallelism of FPGA devices. Moreover, since the proposed template can be instantiated with different parameters, we also propose a design metric, the expansion rate, to help the designer in the estimation of the efficiency and performance of the different instances, making it possible to select the right one before the implementation phase. We finally show, by means of experimental results, how the proposed analysis and parallelization approach leads to the design of efficient and high-performance FPGA-based implementations that are orders of magnitude faster than the state-of-the-art ones